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On state reduction of incompletely specified finite state machines.

, and . Comput. Electr. Eng., 33 (1): 58-69 (2007)

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Testing Finite State Machines Based on a Structural Coverage Metric ., and . ITC, page 773-780. IEEE Computer Society, (2002)Maximum Likelihood Estimation for Yield Analysis., and . DFT, page 149-158. IEEE Computer Society, (1996)Defect Classes - An Overdue Paradigm for CMOS IC., , , and . ITC, page 413-425. IEEE Computer Society, (1994)Incorporating Physical Design-for-Test into Routing., and . ITC, page 685-693. IEEE Computer Society, (1997)Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault Analysis., and . ITC, page 475-484. IEEE Computer Society, (1988)Carafe: an inductive fault analysis tool for CMOS VLSI circuits., and . VTS, page 92-98. IEEE Computer Society, (1993)Physical design for testability for bridges in CMOS circuits.. VTS, page 290-295. IEEE Computer Society, (1993)A methodolgy for characterizing cell testability., and . VTS, page 384-390. IEEE Computer Society, (1997)Using Temporal Constraints for Eliminating Crosstalk Candidates for Design and Test., and . VTS, page 80-85. IEEE Computer Society, (1999)A Systematic DFT Procedure for Library Cells., , and . VTS, page 460-466. IEEE Computer Society, (1999)