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Disambiguation of "Iyer, Ravi R."

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A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs.

, , , , , , , , and . ISVLSI, page 480-485. IEEE Computer Society, (2014)

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Samatha Ravipati

Fausto Ravida

Somasundaram Ravindran

Holger Raviol

Jewgeni Ravik

 

Other publications of authors with the same name

QoS policies and architecture for cache/memory in CMP platforms., , , , , , , , and . SIGMETRICS, page 25-36. ACM, (2007)RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization., , , , , , , , , and 1 other author(s). NetSoft, page 335-343. IEEE, (2020)SpliceNP: a TCP splicer using a network processor., , , and . ANCS, page 135-143. ACM, (2005)Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family., , , , , , and . HPCA, page 657-668. IEEE Computer Society, (2016)Hardware Support for Bulk Data Movement in Server Platforms., , , , and . ICCD, page 53-60. IEEE Computer Society, (2005)Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors., , and . IPDPS, page 721-728. IEEE Computer Society, (2000)Comparing the memory system performance of the HP V-class and SGI Origin 2000 multiprocessors using microbenchmarks and scientific applications., , , and . International Conference on Supercomputing, page 339-347. ACM, (1999)Rate-based QoS techniques for cache/memory in CMP platforms., , , , , and . ICS, page 479-488. ACM, (2009)Reducing cache and TLB power by exploiting memory region and privilege level semantics., , , , , , and . J. Syst. Archit., 59 (6): 279-295 (2013)Towards hybrid last level caches for chip-multiprocessors., , , and . SIGARCH Comput. Archit. News, 36 (2): 56-63 (2008)