( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Energy-efficient dot product computation using a switched analog circuit architecture.

, , , и . ISLPED, стр. 315-318. ACM, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Naresh Yallapragada

Uma-Naresh Niranjan

Naresh Bikash Dasgupta

Naresh Reddy Thumati

Naresh Chandra Varshneya

 

Другие публикации лиц с тем же именем

A voltage overscaled low-power digital filter IC., и . IEEE J. Solid State Circuits, 39 (2): 388-391 (2004)A Variation-Tolerant In-Memory Machine Learning Classifier via On-Chip Training., , и . IEEE J. Solid State Circuits, 53 (11): 3163-3173 (2018)Analytical estimation of signal transition activity from word-level statistics., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (7): 718-733 (1997)Area-efficient high-throughput MAP decoder architectures., , и . IEEE Trans. Very Large Scale Integr. Syst., 13 (8): 921-933 (2005)A 19.4 nJ/decision 364K decisions/s in-memory random forest classifier in 6T SRAM array., , и . ESSCIRC, стр. 263-266. IEEE, (2017)A sphere decoding approach for the vector Viterbi algorithm., , , и . ACSCC, стр. 114-118. IEEE, (2012)A pipelined adaptive NEXT canceller., и . IEEE Trans. Signal Process., 46 (8): 2252-2258 (1998)Noise-tolerant dynamic circuit design., и . ISCAS (1), стр. 549-552. IEEE, (1999)Roundoff error analysis of the pipelined ADPCM coder., и . ISCAS, стр. 886-889. IEEE, (1993)Pipelined Adaptive IIR Filter Architecture., и . ISCAS, стр. 558-561. IEEE, (1995)