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Disambiguation of "Sharkey, Joseph J."

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Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization.

, , , and . PACS, volume 3471 of Lecture Notes in Computer Science, page 15-29. Springer, (2004)

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Simon J Joseph

Heinrich J J Mieschendahl

Norbert J J Bock

J J M Ramakers

Ulrich J J Longerich

 

Other publications of authors with the same name

Evaluating design tradeoffs in on-chip power management for CMPs., , and . ISLPED, page 44-49. ACM, (2007)Efficient instruction schedulers for SMT processors., and . HPCA, page 288-298. IEEE Computer Society, (2006)Reducing Delay and Power Consumption of the Wakeup Logic Through Instruction Packing and Tag Memoization., , , and . PACS, volume 3471 of Lecture Notes in Computer Science, page 15-29. Springer, (2004)Instruction packing: reducing power and delay of the dynamic scheduling logic., , , and . ISLPED, page 30-35. ACM, (2005)Selective writeback: exploiting transient values for energy-efficiency and performance., , , and . ISLPED, page 37-42. ACM, (2006)Trade-Offs in Transient Fault Recovery Schemes for Redundant Multithreaded Processors., , , , and . HiPC, volume 4297 of Lecture Notes in Computer Science, page 135-147. Springer, (2006)SPARTAN: speculative avoidance of register allocations to transient values for performance and energy efficiency., , , and . PACT, page 265-274. ACM, (2006)Address-Value Decoupling for Early Register Deallocation., , , and . ICPP, page 337-346. IEEE Computer Society, (2006)Selective Writeback: Reducing Register File Pressure and Energy Consumption., , , and . IEEE Trans. Very Large Scale Integr. Syst., 16 (6): 650-661 (2008)Instruction packing: Toward fast and energy-efficient instruction scheduling., , , and . ACM Trans. Archit. Code Optim., 3 (2): 156-181 (2006)