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Другие публикации лиц с тем же именем

Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis., , и . IOLTS, стр. 232-235. IEEE, (2018)Autonomous temperature control technique in VLSI circuits through logic replication., и . IET Comput. Digit. Tech., 3 (1): 62-71 (2009)Efficient Functional Locking of Behavioral IPs., и . MWSCAS, стр. 639-642. IEEE, (2020)Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 3939-3950 (ноября 2023)Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs., и . FPT, стр. 193-196. IEEE, (2016)Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations., и . ICCD, стр. 524-531. IEEE, (2019)Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models., и . ICCAD, стр. 1-8. ACM, (2019)Precision tunable RTL macro-modelling cycle-accurate power estimation., и . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR., и . DATE, стр. 1-6. IEEE, (2023)Investigation and Optimization of Pin Multiplexing in High-Level Synthesis., , и . ACM Great Lakes Symposium on VLSI, стр. 427-430. ACM, (2018)