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MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors.

, and . Microprocess. Microsystems, (2024)

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Design and Optimization of Reliable Hardware Accelerators: Leveraging the Advantages of High-Level Synthesis., , and . IOLTS, page 232-235. IEEE, (2018)Low Power Design of Runtime Reconfigurable FPGAs through Contexts Approximations., and . ICCD, page 524-531. IEEE, (2019)Approximating Behavioral HW Accelerators through Selective Partial Extractions onto Synthesizable Predictive Models., and . ICCAD, page 1-8. ACM, (2019)Fast and Inexpensive High-Level Synthesis Design Space Exploration: Machine Learning to the Rescue., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 3939-3950 (November 2023)Autonomous temperature control technique in VLSI circuits through logic replication., and . IET Comput. Digit. Tech., 3 (1): 62-71 (2009)Learning from the Past: Efficient High-level Synthesis Design Space Exploration for FPGAs., and . ACM Trans. Design Autom. Electr. Syst., 27 (4): 34:1-34:23 (2022)Precision tunable RTL macro-modelling cycle-accurate power estimation., and . IET Comput. Digit. Tech., 5 (2): 95-103 (2011)Hardware Trojan avoidance and detection for dynamically re-configurable FPGAs., and . FPT, page 193-196. IEEE, (2016)Efficient Functional Locking of Behavioral IPs., and . MWSCAS, page 639-642. IEEE, (2020)MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileR., and . DATE, page 1-6. IEEE, (2023)