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A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS.

F. Zhong, S. Quan, W. Liu, P. Aziz, T. Jing, J. Dong, C. Desai, H. Gao, M. Garcia, G. Hom, T. Huynh, H. Kimura, R. Kothari, L. Li, C. Liu, S. Lowrie, K. Ling, A. Malipatil, R. Narayan, T. Prokop, C. Palusa, A. Rajashekara, A. Sinha, C. Zhong, and E. Zhang. IEEE J. Solid State Circuits, 46 (12): 3126-3139 (2011)

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Pervez Patel

Pervez Zamurrad Janjua

Hassan Azizian

Majid Azizi

Farah Aziz

Other publications of authors with the same name

Analysis of a class of decimated clock/data recovery architectures for serial links.P. Aziz, and A. Malipatil. ISCAS, page 1175-1178. IEEE, (2013)Multi band sigma delta analog to digital conversion.P. Aziz, H. Sorensen, and J. der Spiegel. ICASSP (3), page 249-252. IEEE Computer Society, (1994)A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS.H. Kimura, P. Aziz, T. Jing, A. Sinha, S. Kotagiri, R. Narayan, H. Gao, P. Jing, G. Hom, A. Liang and 13 other author(s). IEEE J. Solid State Circuits, 49 (12): 3091-3103 (2014)A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS.S. Quan, F. Zhong, W. Liu, P. Aziz, T. Jing, J. Dong, C. Desai, H. Gao, M. Garcia, G. Hom and 15 other author(s). ISSCC, page 348-350. IEEE, (2011)A class of downsampled floating tap DFE architectures with application to serial links.P. Aziz, H. Kimura, A. Malipatil, and S. Kotagiri. ISCAS, page 325-328. IEEE, (2012)Adaptation algorithms for a class of continuous time analog equalizers with application to serial links.P. Aziz, and A. Malipatil. ISCAS, page 1383-1386. IEEE, (2011)A rate 16/17 punctured MTR block code.P. Aziz, N. Sayiner, and V. Annampedu. ICC, page 1643-1647. IEEE, (1999)Performance of Complex Noise Transfer Functions in Bandpass and Multi Band Sigma Delta Systems.P. Aziz, H. Sorensen, and J. der Spiegel. ISCAS, page 641-644. IEEE, (1995)Shift register multi-phase clock based downsampled floating tap DFE for serial links.P. Aziz, H. Kimura, A. Malipatil, S. Kotagiri, G. Chan, and H. Gao. ISCAS, page 2469-2472. IEEE, (2014)2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS.H. Kimura, P. Aziz, T. Jing, A. Sinha, R. Narayan, H. Gao, P. Jing, G. Hom, A. Liang, E. Zhang and 13 other author(s). ISSCC, page 38-39. IEEE, (2014)

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Disambiguation of "Aziz, Pervez M."