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Ternary Competitive to Binary: A Novel Implementation of Ternary Logic Using Depletion-mode and Conventional MOSFETs., , , , , , and . ISMVL, page 21-26. IEEE, (2022)A Novel Processing Unit and Architecture for Process-In Memory (PIM) in NAND Flash Memory., , , and . ISOCC, page 127-128. IEEE, (2022)HFGCN: High-speed and Fully-optimized GCN Accelerator., , , , , , , , , and 1 other author(s). ISQED, page 1-7. IEEE, (2023)High-throughput PIM (Processing in-Memory) for DRAM using Bank-level Pipelined Architecture., , , , , and . ISOCC, page 101-102. IEEE, (2023)Signal integrity analysis and optimization for 3D ICs., , and . ISQED, page 42-49. IEEE, (2011)A Practical Implementation of the Ternary Logic Using Memristors and MOSFETs., , , , , and . ISMVL, page 183-188. IEEE, (2021)FS2K: A Forksheet FET Technology Library and a Study of VLSI Prediction for 2nm and Beyond., , , , , , , , and . ISCAS, page 1-5. IEEE, (2024)A Study on Optimizing Pin Accessibility of Standard Cells in the Post-3 nm Node., , and . ISLPED, page 16:1-16:6. ACM, (2022)Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICs., , , and . ICCAD, page 649-655. IEEE, (2015)A Prediction Scheme in Spiking Neural Network (SNN) Hardware for Ultra-low Power Consumption., and . ISOCC, page 310-311. IEEE, (2020)