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A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips.

, , , , and . VDAT, volume 892 of Communications in Computer and Information Science, page 446-459. Springer, (2018)

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1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing., , , , , , , , , and 1 other author(s). ISCAS, page 1-5. IEEE, (2023)A Novel Fault-Tolerant Routing Technique for Mesh-of-Tree based Network-on-Chip Design., , , , , and . TENCON, page 2378-2383. IEEE, (2018)REACT: a heterogeneous reconfigurable neural network accelerator with software-configurable NoCs for training and inference on wearables., , , , , and . DAC, page 1291-1296. ACM, (2022)A Novel Fault-Tolerant Routing Algorithm for Mesh-of-Tree Based Network-on-Chips., , , , and . VDAT, volume 892 of Communications in Computer and Information Science, page 446-459. Springer, (2018)Blockchain Machine: A Network-Attached Hardware Accelerator for Hyperledger Fabric., , , , , , and . ICDCS, page 258-268. IEEE, (2022)Network-on-Chip-Centric Accelerator Architectures for Edge AI Computing., , , , , and . ISOCC, page 243-244. IEEE, (2022)Fault Tolerant Routing Methodology for Mesh-of-Tree based Network-on-Chips using Local Reconfiguration., , , , and . HPCS, page 570-576. IEEE, (2018)NOVA: NoC-based Vector Unit for Mapping Attention Layers on a CNN Accelerator., , , and . DATE, page 1-6. IEEE, (2024)Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable Architecture., , , , and . VLSID, page 527-528. IEEE, (2019)