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Test Roles in Diagnosis and Silicon Debug., , , , , , и . ATS, стр. 367. IEEE, (2007)ATREX : Design for Testability System for Mega Gate LSIs., , , , , и . Asian Test Symposium, стр. 126-. IEEE Computer Society, (1997)A Study of Capture-Safe Test Generation Flow for At-Speed Testing., , , , , , , , , и 1 other автор(ы). IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (7): 1309-1318 (2010)Test Challenge for Deep Sub-micron Era - Test & Diagnosis Platform: STARCAD-Clouseau.. DFT, стр. 227. IEEE Computer Society, (2010)Small Delay Fault Model for Intra-Gate Resistive Open Defects., , , , , , и . VTS, стр. 27-32. IEEE Computer Society, (2009)An Automatic Test Generation System for Large Scale Gate Arrays., , , , и . COMPCON, стр. 445-451. IEEE Computer Society, (1986)At-Speed Testing with Timing Exceptions and Constraints-Case Studies., , , , , , , , , и . ATS, стр. 153-162. IEEE, (2006)Post-BIST Fault Diagnosis for Multiple Faults., , , , , , и . IEICE Trans. Inf. Syst., 91-D (3): 771-775 (2008)ASIC CAD system based on hierarchical design-for-testability., , , и . ITC, стр. 404-409. IEEE Computer Society, (1990)A Capture-Safe Test Generation Scheme for At-Speed Scan Testing., , , , , , , , , и 1 other автор(ы). ETS, стр. 55-60. IEEE Computer Society, (2008)