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Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking.

, , , , , , , and . FMCAD, volume 1166 of Lecture Notes in Computer Science, page 19-33. Springer, (1996)

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Advanced techniques for RTL debugging., , , and . DAC, page 362-367. ACM, (2003)Equivalence checking of integer multipliers., and . ASP-DAC, page 169-174. ACM, (2001)Algorithms for compacting error traces., and . ASP-DAC, page 99-103. ACM, (2003)Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking., , , , , , , and . FMCAD, volume 1166 of Lecture Notes in Computer Science, page 19-33. Springer, (1996)Space- and Time-Efficient BDD Construction via Working Set Control., , , and . ASP-DAC, page 423-432. IEEE, (1998)PHDD: an efficient graph representation for floating point circuit verification., and . ICCAD, page 2-7. IEEE Computer Society / ACM, (1997)Verification of Arithmetic Circuits with Binary Moment Diagrams., and . DAC, page 535-541. ACM Press, (1995)Verification of Floating-Point Adders., and . CAV, volume 1427 of Lecture Notes in Computer Science, page 488-499. Springer, (1998)ACV: an arithmetic circuit verifier., and . ICCAD, page 361-365. IEEE Computer Society / ACM, (1996)