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Verification of Circuits Described in VHDL through Extraction of Design Intent.

, , , и . VLSI Design, стр. 417-420. IEEE Computer Society, (1994)

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Jacob Jacob

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Abraham Wilentschuk

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Günter Abraham

 

Другие публикации лиц с тем же именем

Research in Reliable VLSI Architectures at the University of Illinois.. FJCC, стр. 890-893. IEEE Computer Society, (1986)Design of Test Pattern Generators for Built-In Test., , и . ITC, стр. 315-319. IEEE Computer Society, (1984)A fast, accurate and simple critical path monitor for improving energy-delay product in DVS systems., и . ISLPED, стр. 391-396. IEEE/ACM, (2011)Forward Recovery Using Checkpointing in Parallel Systems., , и . ICPP (1), стр. 272-275. Pennsylvania State University Press, (1990)Abstraction of data path registers for multilevel verification of large circuits., , , и . Great Lakes Symposium on VLSI, стр. 11-14. IEEE, (1994)Design and evaluation of fault tolerance techniques for highly parallel architectures.. Great Lakes Symposium on VLSI, IEEE, (1991)An oscillation-based test structure for timing information extraction., , , и . VTS, стр. 74-79. IEEE Computer Society, (2012)Average Interconnection Length and Interconnection Distribution Based on Rent's Rule., и . DAC, стр. 574-577. ACM Press, (1989)A Novel Approach to Accurate Timing Verification Using RTL Descriptions., и . DAC, стр. 638-641. ACM Press, (1989)Delay Defect Diagnosis Methodology Using Path Delay Measurements., , и . IEICE Trans. Electron., 98-C (10): 991-994 (2015)