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Disambiguation of "Hsu, Steven"

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A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition.

, , , , , , , , , , , and . VLSI Circuits, page 234-. IEEE, (2019)

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Eric Hsu

Yüanfang Hsü

Oscar Hsu

Eugene Hsu

Allen Hsu

 

Other publications of authors with the same name

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS., , , , , , , , , and . ESSCIRC, page 210-213. IEEE, (2010)On-Chip High-Resolution Timing Characterization Circuits for Memory IPs., , , , , , and . ESSCIRC, page 377-380. IEEE, (2022)Near-threshold voltage (NTV) design: opportunities and challenges., , , , , and . DAC, page 1153-1158. ACM, (2012)Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS., , , , , , , , , and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision floating-point register file and shuffler in 32nm CMOS., , , , , , , and . VLSIC, page 118-119. IEEE, (2012)A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS., , , , , , , and . VLSI Circuits, page 1-2. IEEE, (2016)A 260mV 468GOPS/W 256b 4-way to 32-way vector shifter with permute-assisted skip in 22nm tri-gate CMOS., , , , , , and . ESSCIRC, page 177-180. IEEE, (2012)A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS., , , , , , , , , and . IEEE J. Solid State Circuits, 52 (4): 940-949 (2017)2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators., , , , , , , , and . VLSI Technology and Circuits, page 22-23. IEEE, (2022)A 7Gbps SCA-Resistant Multiplicative-Masked AES Engine in Intel 4 CMOS., , , , , , , and . VLSI Technology and Circuits, page 138-139. IEEE, (2022)