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Multi-bit sigma-delta TDC architecture with self-calibration.

S. Uemori, M. Ishii, H. Kobayashi, Y. Doi, O. Kobayashi, T. Matsuura, K. Niitsu, Y. Arakawa, D. Hirabayashi, Y. Yano, T. Gake, N. Takai, and T. Yamaguchi. APCCAS, page 671-674. IEEE, (2012)

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Yuji Kera

Michitami Yano

Thaise Yano

Hisashi Yano

Maxim Yanovskiy

Other publications of authors with the same name

A 5-ms Error, 22-μA Photoplethysmography Sensor using Current Integration Circuit and Correlated Double Sampling.Y. Yano. EMBC, page 5566-5569. IEEE, (2018)Multi-bit sigma-delta TDC architecture with self-calibration.S. Uemori, M. Ishii, H. Kobayashi, Y. Doi, O. Kobayashi, T. Matsuura, K. Niitsu, Y. Arakawa, D. Hirabayashi, Y. Yano and 3 other author(s). APCCAS, page 671-674. IEEE, (2012)Sampling Rate Reduction for Wearable Heart Rate Variability Monitoring.Y. Nishikawa, S. Izumi, Y. Yano, H. Kawaguchi, and M. Yoshimoto. ISCAS, page 1-5. IEEE, (2018)An IoT Sensor Node SoC with Dynamic Power Scheduling for Sustainable Operation in Energy Harvesting Environment.Y. Yano, S. Yoshida, S. Izumi, H. Kawaguchi, T. Hirose, M. Miyahara, T. Someya, K. Okada, I. Akita, Y. Kurui and 2 other author(s). A-SSCC, page 267-270. IEEE, (2019)A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS.I. Hayashi, T. Amano, N. Watanabe, Y. Yano, Y. Kuroda, M. Shirata, K. Dosaka, K. Nii, H. Noda, and H. Kawai. IEEE J. Solid State Circuits, 48 (11): 2671-2680 (2013)Associative memory with fully parallel nearest-Manhattan-distance search for low-power real-time single-chip applications.Y. Yano, T. Koide, and H. Mattausch. ASP-DAC, page 543-544. IEEE Computer Society, (2004)2D Sliced Packet Buffer with traffic volume and buffer occupancy adaptation for power saving.K. Okuda, S. Ata, Y. Kuroda, Y. Yano, H. Iwamoto, K. Inoue, and I. Oka. CCNC, page 97-105. IEEE, (2013)Energy-efficient high-speed search engine using a multi-dimensional TCAM architecture with parallel pipelined subdivided structure.M. Nawa, K. Okuda, S. Ata, Y. Kuroda, Y. Yano, H. Iwamoto, K. Inoue, and I. Oka. CCNC, page 309-314. IEEE, (2016)An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing.D. Watanabe, Y. Yano, S. Izumi, H. Kawaguchi, K. Takeuchi, T. Hiramoto, S. Iwai, M. Murakata, and M. Yoshimoto. AICAS, page 305-309. IEEE, (2020)A slice structure using the management of network traffic prediction for green IT.Y. Yano, H. Iwamoto, Y. Kuroda, S. Ohtani, S. Ata, and K. Inoue. HPSR, page 250-255. IEEE, (2012)

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Disambiguation of "Yano, Yuji"

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Multi-bit sigma-delta TDC architecture with self-calibration.

Please choose a person to relate this publication to

Yuji Kera

Michitami Yano

Thaise Yano

Hisashi Yano

Maxim Yanovskiy

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Yano, Yuji"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Multi-bit sigma-delta TDC architecture with self-calibration.

Please choose a person to relate this publication to

Yuji Kera

Michitami Yano

Thaise Yano

Hisashi Yano

Maxim Yanovskiy

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Multi-bit sigma-delta TDC architecture with self-calibration.