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Disambiguation of "Vemuri, Ranga"

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RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks.

, , , , , and . MWSCAS, page 511-515. IEEE, (2023)

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Janki Rangatia

Sripriya Rangarajan

Kiril Rangatscheff

Hiranmayi Ranganathan

Palani Murugan Rangasamy

 

Other publications of authors with the same name

Simulation based architectural power estimation for PLA-based controllers., and . ISLPED, page 121-124. IEEE, (1996)Scheduling for low power under resource and latency constraints., and . ISCAS, page 53-56. IEEE, (2000)Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks., , and . iSES, page 445-450. IEEE, (2022)SoC Trust Validation Using Assertion-Based Security Monitors., , , and . ISQED, page 496-503. IEEE, (2021)Moment-driven coupling-aware routing methodology., and . ACM Great Lakes Symposium on VLSI, page 390-395. ACM, (2005)Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits., , and . ACM Great Lakes Symposium on VLSI, page 482-487. ACM, (2005)LiPaR: A light-weight parallel router for FPGA-based networks-on-chip., , , and . ACM Great Lakes Symposium on VLSI, page 452-457. ACM, (2005)Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis., , and . VLSI Design, page 589-596. IEEE Computer Society, (1999)On-Line Synthesis for Partially Reconfigurable FPGAs., and . VLSI Design, page 663-668. IEEE Computer Society, (2005)Formal Verification of Synthesized Mixed Signal Designs Using *BMDs., and . VLSI Design, page 84-. IEEE Computer Society, (2000)