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Disambiguation of "Ranganathan, Nagarajan"

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A Framework for Power-Gating Functional Units in Embedded Microprocessors.

, , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (11): 1640-1649 (2009)

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Hiranmayi Ranganathan

Sujatha Nagarajan

Vijayasarathi Nagarajan

Manju Nagarajan

Nagarajan Periasamy

 

Other publications of authors with the same name

Transient power minimization through datapath scheduling in multiple supply voltage environment., , and . ICECS, page 300-303. IEEE, (2003)A framework for energy and transient power reduction during behavioral synthesis., and . IEEE Trans. Very Large Scale Integr. Syst., 12 (6): 562-572 (2004)A high speed systolic architecture for labeling connected components in an image., , and . IEEE Trans. Syst. Man Cybern., 25 (3): 415-423 (1995)Efficient reversible NOR gates and their mapping in optical computing domain., , and . Microelectron. J., 45 (6): 825-834 (2014)Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits., , and . VLSID, page 545-550. IEEE Computer Society, (2014)Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS., and . VLSID, page 470-475. IEEE Computer Society, (2014)Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation., and . VLSI Design, page 766-769. IEEE Computer Society, (2006)Run-time power-gating in caches of GPUs for leakage energy savings., , and . DATE, page 300-303. IEEE, (2012)Mach-Zehnder interferometer based design of all optical reversible binary adder., , and . DATE, page 721-726. IEEE, (2012)A linear systolic algorithm and architecture for convex bipartite matching., and . HiPC, page 379-384. IEEE Computer Society, (1996)