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Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power., и . ISLPED, стр. 99-104. ACM, (2008)Transient power minimization through datapath scheduling in multiple supply voltage environment., , и . ICECS, стр. 300-303. IEEE, (2003)A framework for energy and transient power reduction during behavioral synthesis., и . IEEE Trans. Very Large Scale Integr. Syst., 12 (6): 562-572 (2004)A high speed systolic architecture for labeling connected components in an image., , и . IEEE Trans. Syst. Man Cybern., 25 (3): 415-423 (1995)DFLAP: a dynamic frequency linear array processor., , и . ICIP (2), стр. 1007-1010. IEEE Computer Society, (1996)Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits., , и . VLSID, стр. 545-550. IEEE Computer Society, (2014)Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOS., и . VLSID, стр. 470-475. IEEE Computer Society, (2014)Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation., и . VLSI Design, стр. 766-769. IEEE Computer Society, (2006)Mach-Zehnder interferometer based design of all optical reversible binary adder., , и . DATE, стр. 721-726. IEEE, (2012)Run-time power-gating in caches of GPUs for leakage energy savings., , и . DATE, стр. 300-303. IEEE, (2012)