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Disambiguation of "Wang, Min-Jer"

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A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC.

, , , , , , , and . CICC, page 1-4. IEEE, (2014)

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Min Wang

Min Wang

Min Wang

Min Wang

Min Wang

 

Other publications of authors with the same name

A 500MHz Random-Access Embedded 1Mb DRAM Macro in Bulk CMOS., , , , , , , , , and 1 other author(s). ISSCC, page 270-271. IEEE, (2008)A HKMG 28nm 1GHz fully-pipelined tile-able 1MB embedded SRAM IP with 1.39mm2 per MB., , , , , , and . CICC, page 1-4. IEEE, (2013)A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 49 (4): 1063-1074 (2014)A memory yield improvement scheme combining built-in self-repair and error correction codes., , , , , , , , , and . ITC, page 1-9. IEEE Computer Society, (2012)High Quality Test Methodology for Highly Reliable Devices., , , and . ITC, page 1-6. IEEE, (2019)Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill., , , , and . ITC-Asia, page 1-6. IEEE, (2020)Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology., , , , , , , , and . CICC, page 1-3. IEEE, (2015)3D-IC interconnect test, diagnosis, and repair., , , and . VTS, page 1-6. IEEE Computer Society, (2013)A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS., , , , , , and . VLSIC, page 62-63. IEEE, (2012)Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs., , , , and . VLSI-DAT, page 1-4. IEEE, (2014)