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Mismatch Insensitive Double-Sampling Quadrature Bandpass SigmaDelta Modulation., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 54-I (12): 2599-2607 (2007)Quadrature Mismatch Shaping Techniques for Fully Differential Circuits., , and . ISCAS, page 3614-3617. IEEE, (2007)Quadrature mismatch shaping with a complex, tree structured DAC., , , and . ISCAS, IEEE, (2006)Redundant signed digit coding in binary weighted DACs., , and . ICECS, page 862-865. IEEE, (2008)An Unconstrained Architecture for High-Order Sigma Delta Force-Feedback Inertial Sensors., , and . ISCAS, page 3063-3066. IEEE, (2007)Design of double-sampling ΣΔ modulation A/D converters with bilinear integrators., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 52-I (4): 715-722 (2005)A 13.5-b 1.2-V micropower extended counting A/D converter., , and . IEEE J. Solid State Circuits, 36 (2): 176-183 (2001)A 250-kHz 94-dB double-sampling ΣΔ modulation A/D converter with a modified noise transfer function., , and . IEEE J. Solid State Circuits, 38 (10): 1657-1662 (2003)An On-Line Calibration Technique for Mismatch Errors in High-Speed DACs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (7): 1873-1883 (2008)A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's., , and . ISCAS, page 1477-1480. IEEE, (2007)