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VLSI design of dual-mode Viterbi/turbo decoder for 3GPP., , , и . ISCAS (2), стр. 773-776. IEEE, (2004)Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules., , , и . ISCAS, стр. 869-872. IEEE, (2007)Low-complexity Recurrent Neural Network-based Polar Decoder with Weight Quantization Mechanism., , , и . CoRR, (2018)A memory-reduced log-MAP kernel for turbo decoder., , и . ISCAS (2), стр. 1032-1035. IEEE, (2005)On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems., , , и . SiPS, стр. 422-427. IEEE, (2006)New Ping-Pong Scheduling for Low-Latency EMD Engine Design in Hilbert-Huang Transform., , и . IEEE Trans. Circuits Syst. II Express Briefs, 60-II (8): 532-536 (2013)High-performance scheduling algorithm for partially parallel LDPC decoder., , и . ICASSP, стр. 3177-3180. IEEE, (2008)A Scalable Extreme Learning Machine (S-ELM) for Class-Incremental ECG-Based User Identification., , и . ISCAS, стр. 1-5. IEEE, (2021)Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem., и . ISCAS, стр. 357-360. IEEE, (2000)Overview of high-efficiency ant colony optimization (ACO)-based adaptive routings for traffic balancing in network-on-chip systems., и . ASICON, стр. 80-83. IEEE, (2017)