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Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules., , , и . ISCAS, стр. 869-872. IEEE, (2007)VLSI design of dual-mode Viterbi/turbo decoder for 3GPP., , , и . ISCAS (2), стр. 773-776. IEEE, (2004)Design methodology for Booth-encoded Montgomery module design for RSA cryptosystem., и . ISCAS, стр. 357-360. IEEE, (2000)A Scalable Extreme Learning Machine (S-ELM) for Class-Incremental ECG-Based User Identification., , и . ISCAS, стр. 1-5. IEEE, (2021)Transport-layer assisted vertical traffic balanced routing for thermal-aware three-dimensional Network-on-Chip systems., , , , и . VLSI-DAT, стр. 1-4. IEEE, (2012)A Triple-mode LDPC Decoder Design for IEEE 802.11n SYSTEM., , , и . ISCAS, стр. 2445-2448. IEEE, (2009)Quality-Aware Signal Processing Mechanism of PPG Signal for Long-Term Heart Rate Monitoring., , и . Sensors, 24 (12): 3901 (июня 2024)High-performance scheduling algorithm for partially parallel LDPC decoder., , и . ICASSP, стр. 3177-3180. IEEE, (2008)Overview of high-efficiency ant colony optimization (ACO)-based adaptive routings for traffic balancing in network-on-chip systems., и . ASICON, стр. 80-83. IEEE, (2017)Low-complexity Recurrent Neural Network-based Polar Decoder with Weight Quantization Mechanism., , , и . CoRR, (2018)