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A Fractional-n subsampling PLL based on a digital-to-time converter., , , and . MIPRO, page 66-71. IEEE, (2016)2.2 A +70dBm IIP3 single-ended electrical-balance duplexer in 0.18um SOI CMOS., , , , , , and . ISSCC, page 1-3. IEEE, (2015)A linear 28nm CMOS digital transmitter with 2×12bit up to LO baseband sampling and -58dBc C-IM3., , , , , and . ESSCIRC, page 379-382. IEEE, (2014)A 9.1-12.7 GHz VCO in 28nm CMOS with a bottom-pinning bias technique for digital varactor stress reduction., , , and . ESSCIRC, page 83-86. IEEE, (2014)A 10-bit, 550-fs step Digital-to-Time Converter in 28nm CMOS., , , and . ESSCIRC, page 79-82. IEEE, (2014)A wideband beamformer for a phased-array 60GHz receiver in 40nm digital CMOS., , , and . ISSCC, page 40-41. IEEE, (2010)An Adaptive Frame Image Sensor with Fine-Grained Power Management for Ultra-Low Power Internet of Things Application., , , , , , , , , and 4 other author(s). ESSCIRC, page 58-61. IEEE, (2018)21.4 A 42mW 230fs-jitter sub-sampling 60GHz PLL in 40nm CMOS., , , , , and . ISSCC, page 366-367. IEEE, (2014)A digitally controlled compact 57-to-66GHz front-end in 45nm digital CMOS., , and . ISSCC, page 492-493. IEEE, (2009)50-to-67GHz ESD-protected power amplifiers in digital 45nm LP CMOS., , , , and . ISSCC, page 382-383. IEEE, (2009)