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Disambiguation of "Chi, Yuze"

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ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture.

, , , , , and . FPGA, page 217-226. ACM, (2017)

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Sotetsu Yuzen

Chi Chu

Hsin Chi

Jian Chi

Ying Chi

 

Other publications of authors with the same name

HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration., , and . FPGA, page 51-57. ACM, (2020)Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver., , , , , and . CoRR, (2022)Design Automation and Optimization for Memory-Bound Application Accelerators.. University of California, Los Angeles, USA, (2021)PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs., , , , , and . FCCM, page 12-22. IEEE, (2023)Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency., , , , , , , and . FPGA, page 311. ACM, (2020)FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search., , , and . FPGA, page 105-110. ACM, (2016)Extending High-Level Synthesis for Task-Parallel Programs., , , , , and . FCCM, page 204-213. IEEE, (2021)StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing., , and . CICC, page 1-8. IEEE, (2022)SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs., , , , , and . CoRR, (2022)TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (7): 2423-2427 (July 2023)