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Другие публикации лиц с тем же именем

Low Complexity SST Viterbi Decoder., и . VTC Fall, стр. 1-2. IEEE, (2006)Finite state machine partitioning for low power., и . ISCAS (1), стр. 306-309. IEEE, (1999)Design and implementation of high-speed arbiter for large scale VOQ crossbar switches., , и . ISCAS (2), стр. 308-311. IEEE, (2003)A thermal-aware application specific routing algorithm for Network-on-Chip design., и . ASP-DAC, стр. 449-454. IEEE, (2011)Low-latency approximate matrix inversion for high-throughput linear pre-coders in massive MIMO., и . VLSI-SoC, стр. 1-5. IEEE, (2016)A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources., , и . VLSI-SoC, стр. 192-195. IEEE, (2011)An efficient Network-on-Chip (NoC) based multicore platform for hierarchical parallel genetic algorithms., , , , , и . NOCS, стр. 17-24. IEEE, (2014)A Two-Staged Adaptive Successive Cancellation List Decoding for Polar Codes., , и . ISCAS, стр. 1-5. IEEE, (2019)A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture., , , , и . CODES+ISSS, стр. 161-170. ACM, (2012)A low power Viterbi decoder implementation using scarce state transition and path pruning scheme for high throughput wireless applications., и . ISLPED, стр. 406-411. ACM, (2006)