From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Fast disjoint transistor networks from BDDs., , , , , и . SBCCI, стр. 137-142. ACM, (2006)Post-processing of supergate networks aiming cell layout optimization., , , , , , и . ISCAS, стр. 1-4. IEEE, (2017)Simulated Annealing Applied to LUT-Based FPGA Technology Mapping., , и . MICAI (Special Session), стр. 23-29. IEEE Computer Society, (2017)Testability Properties of BDDs., , , , и . SBCCI, стр. 83-88. IEEE Computer Society, (2002)Transistor Placement for Automatic Cell Synthesis through Boolean Satisfiability., , , , и . ISCAS, стр. 1-5. IEEE, (2020)NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements., , , , , и . SBCCI, стр. 1-6. IEEE, (2012)A Novel Sizing Method Aiming Security Against Differential Power Analysis., , , , , и . ICECS, стр. 429-432. IEEE, (2018)A post-processing methodology to improve the automatic design of CMOS gates at layout-level., , , , , , и . ICECS, стр. 42-45. IEEE, (2017)Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing., , , , , , , , и . ISCAS, стр. 1-5. IEEE, (2019)Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool., , , , , и . LASCAS, стр. 355-358. IEEE, (2016)