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A High Throughput and Data Reuse Architecture for H.264/AVC Deblocking Filter., , , и . APCCAS, стр. 1260-1263. IEEE, (2006)Design and implementation of the tree-based fuzzy logic controller., и . IEEE Trans. Syst. Man Cybern. Part B, 27 (3): 475-487 (1997)Novel 10-Bit Impedance-to-Digital Converter for Electrochemical Impedance Spectroscopy Measurements., , , , и . IEEE Trans. Biomed. Circuits Syst., 11 (2): 370-379 (2017)A new level converter for low-power applications., , и . ISCAS (1), стр. 113-116. IEEE, (2001)A 1-v 9-bit, 2.5-Msample/s pipelined ADC with merged switched-opamp and opamp-sharing techniques., и . ISCAS (3), стр. 1972-1975. IEEE, (2005)System level design of a spatio-temporal video resampling architecture., , , и . ISCAS, стр. 2797-2800. IEEE, (2008)A scalable sorting architecture based on maskable WTA/MAX circuit., , и . ISCAS (4), стр. 209-212. IEEE, (2002)A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach., , , и . ISLPED, стр. 252-256. ACM, (2004)A microfluidic and potentiostatic sensor integrated with neopterin-imprinted poly(ethylene-c0-vinyl alcohol) based electrode., , , , , , , и . NEMS, стр. 575-578. IEEE, (2011)Performance-directed compaction for VLSI symbolic layouts., , , и . Comput. Aided Des., 27 (1): 65-74 (1995)