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Disambiguation of "Fayyazi, Arash"

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Scalable Superconductor Neuron with Ternary Synaptic Connections for Ultra-Fast SNN Hardware.

, , , , , and . CoRR, (2024)

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Afshin Fayyazi

Laila Arash

Haris Arash-Asish

Arash Mehdiani

Arash Alavi

 

Other publications of authors with the same name

A Hybrid Framework for Functional Verification using Reinforcement Learning and Deep Learning., , , , , and . ACM Great Lakes Symposium on VLSI, page 367-370. ACM, (2019)NullaNet Tiny: Ultra-low-latency DNN Inference Through Fixed-function Combinational Logic., , , , , and . FCCM, page 266-267. IEEE, (2021)CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered Sparsity., , , , and . ISVLSI, page 465-470. IEEE, (2019)qCG: A Low-Power Multi-Domain SFQ Logic Design and Verification Framework., , and . ICCD, page 446-449. IEEE, (2019)OCTAN: An On-Chip Training Algorithm for Memristive Neuromorphic Circuits., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (12): 4687-4698 (2019)Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators., , , and . ISLPED, page 3:1-3:6. ACM, (2022)SEERAD: A high speed yet energy-efficient rounding-based approximate divider., , , , , and . DATE, page 1481-1484. IEEE, (2016)Efficient Compilation and Mapping of Fixed Function Combinational Logic onto Digital Signal Processors Targeting Neural Network Inference and Utilizing High-level Synthesis., , , and . ACM Trans. Reconfigurable Technol. Syst., 16 (2): 17:1-17:25 (June 2023)VeriSFQ: A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology., , , , , and . ISQED, page 224-230. IEEE, (2019)PHAX: Physical Characteristics Aware Ex-Situ Training Framework for Inverter-Based Memristive Neuromorphic Circuits., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 37 (8): 1602-1613 (2018)