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An Efficient GCNs Accelerator Using 3D-Stacked Processing-in-Memory Architectures.

R. Wang, A. Hu, L. Zheng, Q. Wang, J. Yuan, H. Liu, L. Yu, X. Liao, and H. Jin. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (5): 1360-1373 (May 2024)

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Wang Wang

Linfang Wang

Investigation of the functions of 53BP1 in DNA demethylationL. Wang. Uni Marburg, (2009)

Paul Wang

Lien Wang

Scheifoo Wang

Other publications of authors with the same name

Distinguishing variance embedding.Q. Wang, J. Li, and X. Wang. Image Vis. Comput., 28 (6): 872-880 (2010)Some non-interior path-following methods based on a scaled central path for linear complementarity problems.Q. Wang, J. Zhao, and Q. Yang. Comput. Optim. Appl., 46 (1): 31-49 (2010)Scalable concurrency debugging with distributed graph processing.L. Zheng, X. Liao, H. Jin, J. Zhao, and Q. Wang. CGO, page 188-199. ACM, (2018)ReaDy: A ReRAM-Based Processing-in-Memory Accelerator for Dynamic Graph Convolutional Networks.Y. Huang, L. Zheng, P. Yao, Q. Wang, H. Liu, X. Liao, H. Jin, and J. Xue. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (11): 3567-3578 (2022)Combining local and global information for nonlinear dimensionality reduction.Q. Wang, and J. Li. Neurocomputing, 72 (10-12): 2235-2241 (2009)ScalaGraph: A Scalable Accelerator for Massively Parallel Graph Processing.P. Yao, L. Zheng, Y. Huang, Q. Wang, C. Gui, Z. Zeng, X. Liao, H. Jin, and J. Xue. HPCA, page 199-212. IEEE, (2022)Spara: An Energy-Efficient ReRAM-Based Accelerator for Sparse Graph Analytics Applications.L. Zheng, J. Zhao, Y. Huang, Q. Wang, Z. Zeng, J. Xue, X. Liao, and H. Jin. IPDPS, page 696-707. IEEE, (2020)GraSU: A Fast Graph Update Library for FPGA-based Dynamic Graph Processing.Q. Wang, L. Zheng, Y. Huang, P. Yao, C. Gui, X. Liao, H. Jin, W. Jiang, and F. Mao. FPGA, page 149-159. ACM, (2021)A Data-Centric Accelerator for High-Performance Hypergraph Processing.Q. Wang, L. Zheng, A. Hu, Y. Huang, P. Yao, C. Gui, X. Liao, H. Jin, and J. Xue. MICRO, page 1326-1341. IEEE, (2022)A General Offloading Approach for Near-DRAM Processing-In-Memory Architectures.D. Chen, H. Jin, L. Zheng, Y. Huang, P. Yao, C. Gui, Q. Wang, H. Liu, H. He, X. Liao and 1 other author(s). IPDPS, page 246-257. IEEE, (2022)

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Disambiguation of "Wang, Qinggang"

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An Efficient GCNs Accelerator Using 3D-Stacked Processing-in-Memory Architectures.

Please choose a person to relate this publication to

Wang Wang

Linfang Wang

Paul Wang

Lien Wang

Scheifoo Wang

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Wang, Qinggang"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML An Efficient GCNs Accelerator Using 3D-Stacked Processing-in-Memory Architectures.

Please choose a person to relate this publication to

Wang Wang

Linfang Wang

Paul Wang

Lien Wang

Scheifoo Wang

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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An Efficient GCNs Accelerator Using 3D-Stacked Processing-in-Memory Architectures.