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HCiM: ADC-Less Hybrid Analog-Digital Compute in Memory Accelerator for Deep Learning Workloads.

, , , and . CoRR, (2024)

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Low-power approximate convolution computing unit with domain-wall motion based "spin-memristor" for image processing applications., , and . DAC, page 21:1-21:6. ACM, (2016)Digital CMOS logic operation in the sub-threshold region., and . ACM Great Lakes Symposium on VLSI, page 107-112. ACM, (2000)A forward body-biased low-leakage SRAM cache: device and architecture considerations., , , and . ISLPED, page 6-9. ACM, (2003)Device optimization for ultra-low power digital sub-threshold operation., , and . ISLPED, page 96-101. ACM, (2004)Low-power DWT-based quasi-averaging algorithm and architecture for epileptic seizure detection., , , , and . ISLPED, page 301-306. ACM, (2010)Thermal analysis of 8-T SRAM for nano-scaled technologies., , and . ISLPED, page 123-128. ACM, (2008)Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator., , and . ISLPED, page 195-200. ACM, (2009)Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates., , and . ISLPED, page 387-390. ACM, (2007)Ultra-low power digital subthreshold logic circuits., and . ISLPED, page 94-96. ACM, (1999)Novel sizing algorithm for yield improvement under process variation in nanometer technology., , and . DAC, page 454-459. ACM, (2004)