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Session 18 overview: Full duplex wireless front-ends., , and . ISSCC, page 312-313. IEEE, (2017)An electrical-balance duplexer for in-band full-duplex with <-85dBm in-band distortion at +10dBm TX-power., , , , and . ESSCIRC, page 176-179. IEEE, (2015)A Design Approach for Power-Optimized Fully Reconfigurable Delta Sigma A/D Converter for 4G Radios., , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (3): 229-233 (2008)A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter., , , and . IEEE J. Solid State Circuits, 50 (5): 1203-1213 (2015)New Associate Editor.. IEEE J. Solid State Circuits, 53 (5): 1243 (2018)A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers., , , , , , , and . IEEE J. Solid State Circuits, 46 (7): 1659-1671 (2011)Correction to Ä 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range"., , , , and . IEEE J. Solid State Circuits, 50 (2): 619 (2015)New Associate Editor.. IEEE J. Solid State Circuits, 52 (4): 887 (2017)A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS., , , , , , and . IEEE J. Solid State Circuits, 43 (12): 2693-2705 (2008)New Associate Editors.. IEEE J. Solid State Circuits, 53 (4): 963-964 (2018)