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P3 (power-performance-process) optimization of nano-CMOS SRAMusing statistical DOE-ILP., , , and . ISQED, page 176-183. IEEE, (2010)Fault-Tolerant Multiprocessor Link and Bus Network Architectures.. IEEE Trans. Computers, 34 (1): 33-45 (1985)Correction: IEEE Transactions on Computers 35(1): 94 (1986).C-testable bit parallel multipliers over GF(2m)., , , and . ACM Trans. Design Autom. Electr. Syst., 13 (1): 5:1-5:18 (2008)Modified Tree Structure for Location Management in Mobile Environments., , and . INFOCOM, page 530-537. IEEE Computer Society, (1995)A new algorithm for order statistic and sorting., and . IEEE Trans. Signal Process., 41 (8): 2688-2694 (1993)Test Generation in Systolic Architecture for Multiplication Over GF(2 m)., , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (9): 1366-1371 (2010)Guest Editorial: Special Issue on "Secure and Fault-Tolerant Embedded Computing"., , and . ACM Trans. Embed. Comput. Syst., 16 (4): 92:1-92:2 (2017)An application specific processor for implementing stack filters., , and . ASAP, page 196-199. IEEE, (1993)Program Fault Tolerance Based on Memory Access Behavior., and . FTCS, page 426-435. IEEE Computer Society, (1991)Modeling of Live Lines and True Sharing in Multi-Cache Memory Systems., , and . ICPP (1), page 326-330. Pennsylvania State University Press, (1990)