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Disambiguation of "Reddy, Sudhakar M."

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GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment.

, , and . VLSI Design, page 533-538. IEEE Computer Society, (2003)

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Sudhakar Peddireddi

Padhmanand Sudhakar

Edamakanti Chandrakanth Reddy

Malgi Prasad Reddy

Martin Reddy

 

Other publications of authors with the same name

Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times., and . FTCS, page 52-59. IEEE Computer Society, (1991)EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits., and . FTCS, page 166-175. IEEE Computer Society, (1993)Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability., , , and . FTCS, page 280-287. IEEE Computer Society, (1992)On the design of robust testable CMOS combinational logic circuits., and . FTCS, page 220-225. IEEE Computer Society, (1988)Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design., , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (4): 42:1-42:19 (2019)Correcting Unidirectional Errors with Nonpositive Hopfield Networks., , and . ICNN, page 2933-2938. IEEE, (1995)A supervised machine learning application in volume diagnosis., , , , , , and . ETS, page 1-6. IEEE, (2019)Volume diagnosis data mining., , and . ETS, page 1-10. IEEE, (2017)Input test data volume reduction based on test vector chains., and . European Test Symposium, page 240. IEEE Computer Society, (2010)Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines., , , , and . DATE, page 1022-1027. IEEE, (2019)