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SOT-MRAM 300mm integration for low power and ultrafast embedded memories., , , , , , , , , and 9 other author(s). CoRR, (2018)Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution., , , , , , , , , and 3 other author(s). IRPS, page 1-5. IEEE, (2021)STT-MRAM array performance improvement through optimization of Ion Beam Etch and MTJ for Last-Level Cache application., , , , , , , , , and 6 other author(s). IMW, page 1-4. IEEE, (2021)SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories., , , , , , , , , and 9 other author(s). VLSI Circuits, page 81-82. IEEE, (2018)Comprehensive Performance and Reliability Assessment of Se-based Selector-Only Memory., , , , , , , , , and 4 other author(s). IRPS, page 7. IEEE, (2024)Integration of epitaxial monolayer MX₂ channels on 300mm wafers via Collective-Die-To-Wafer (CoD2W) transfer., , , , , , , , , and 10 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)First demonstration of Two Metal Level Semi-damascene Interconnects with Fully Self-aligned Vias at 18MP., , , , , , , , , and 5 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2022)Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm., , , , , , , , , and 14 other author(s). VLSI Technology and Circuits, page 292-293. IEEE, (2022)Lowest IOFF < 3×10-21 A/μm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT., , , , , , , , , and 1 other author(s). VLSI Technology and Circuits, page 1-2. IEEE, (2023)Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control., , , , , , , , , and 10 other author(s). ICICDT, page 88. IEEE, (2022)