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Disambiguation of "Savanth, Anand"

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A Sub-nW/kHz Relaxation Oscillator With Ratioed Reference and Sub-Clock Power Gated Comparator.

, , , , and . IEEE J. Solid State Circuits, 54 (11): 3097-3106 (2019)

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Davinder Kumar Anand

Amar Frank Anand

Madhankumar Anandhakrishnan

Anand Raghavachar

Anand Roy

 

Other publications of authors with the same name

A 50nW Voltage Monitor Scheme for Minimum Energy Sensor Systems., , , , and . VLSID, page 81-86. IEEE Computer Society, (2017)Design challenges for near and sub-threshold operation: A case study with an ARM Cortex-M0+ based WSN subsystem., , , , and . PATMOS, page 56-63. IEEE, (2016)Comparing NVM Technologies through the Lens of Intermittent Computation., , , and . ENSsys@SenSys, page 77-78. ACM, (2020)Improving the Forward Progress of Transient Systems., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 40 (3): 444-452 (2021)5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stability., , , , and . ISSCC, page 96-97. IEEE, (2017)Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS., , , , , and . IEEE J. Solid State Circuits, 54 (2): 550-559 (2019)A Subthreshold ARM Cortex-M0+ Subsystem in 65 nm CMOS for WSN Applications with 14 Power Domains, 10T SRAM, and Integrated Voltage Regulator., , , , , and . IEEE J. Solid State Circuits, 51 (1): 31-44 (2016)Evaluation and analysis of single-phase clock flip-flops for NTV applications., , , , , and . PATMOS, page 1-6. IEEE, (2017)Pragmatic Memory-System Support for Intermittent Computing Using Emerging Nonvolatile Memory., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (1): 95-108 (2023)Integrated Reciprocal Conversion With Selective Direct Operation for Energy Harvesting Systems., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (9): 2370-2379 (2017)