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A Class of Graphs for Fault-Tolerant Processor Interconnections., and . ICDCS, page 448-460. IEEE Computer Society, (1984)On the Design of Testable Domino PLAs., and . ITC, page 567-573. IEEE Computer Society, (1985)Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes., and . IEEE Trans. Computers, 25 (9): 945-949 (1976)On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences., and . IEEE Trans. Computers, 45 (1): 20-32 (1996)A Fault-Tolerant Communication Architecture for Distributed Systems., and . IEEE Trans. Computers, 31 (9): 863-870 (1982)A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set., and . IEEE Trans. Computers, 51 (11): 1282-1293 (2002)On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines., and . IEEE Trans. Computers, 49 (1): 88-94 (2000)On Totally Self-Checking Checkers for Separable Codes., and . IEEE Trans. Computers, 26 (8): 737-744 (1977)On the Design of Pseudoexhaustive Testable PLA's., and . IEEE Trans. Computers, 37 (4): 468-472 (1988)Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units., , and . IEEE Trans. Computers, 53 (1): 83-88 (2004)