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Windows CE for a reconfigurable system-on-a-chip processor., and . FPT, page 201-207. IEEE, (2004)Dynamic memory optimization using pool allocation and prefetching., , and . SIGARCH Comput. Archit. News, 33 (5): 27-32 (2005)Optimizing floating point operations in Scheme.. Comput. Lang., 25 (2): 89-112 (1999)Tensorox: Accelerating GPU Applications via Neural Approximation on Unused Tensor Cores., and . IEEE Trans. Parallel Distributed Syst., 33 (2): 429-443 (2022)Simeuro: A Hybrid CPU-GPU Parallel Simulator for Neuromorphic Computing Chips., , , , , , , , , and 1 other author(s). IEEE Trans. Parallel Distributed Syst., 34 (10): 2767-2782 (October 2023)Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers., and . IEEE Trans. Computers, 43 (3): 278-294 (1994)NC-Net: Efficient Neuromorphic Computing Using Aggregated Subnets on a Crossbar-Based Architecture With Nonvolatile Memory., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (9): 2957-2969 (2022)Guest Editorial - BSN2010 Special Issue., , and . IEEE Trans. Biomed. Circuits Syst., 5 (4): 305-306 (2011)DTNN: Energy-efficient Inference with Dendrite Tree Inspired Neural Networks for Edge Vision Applications., , , , , and . CoRR, (2021)DeepFire2: A Convolutional Spiking Neural Network Accelerator on FPGAs., , , , , , , and . CoRR, (2023)