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Disambiguation of "Zambreno, Joseph"

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Microarchitectures for Managing Chip Revenues under Process Variations.

, , , , and . IEEE Comput. Archit. Lett., 6 (2): 29-32 (2007)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Joseph Stegemann

Joseph Safferling

Joseph Specht

Joseph Müller

Joseph Demleitner

 

Other publications of authors with the same name

Improving System Predictability and Performance via Hardware Accelerated Data Structures., , , , , , and . ICCS, volume 9 of Procedia Computer Science, page 1197-1205. Elsevier, (2012)RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing., , , , and . IEEE Trans. Parallel Distributed Syst., 27 (10): 3029-3043 (2016)Towards Reverse Engineering Controller Area Network Messages Using Machine Learning., , and . WF-IoT, page 1-6. IEEE, (2020)An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (1): 113-123 (2012)Scalable FastMDP for Pre-departure Airspace Reservation and Strategic De-conflict., , and . CoRR, (2020)Enhancing Compiler Techniques for Memory Energy Optimizations., , and . EMSOFT, volume 2491 of Lecture Notes in Computer Science, page 364-381. Springer, (2002)Securing Multimedia Content Using Joint Compression and Encryption., , and . IEEE Multim., 20 (4): 50-61 (2013)A Reconfigurable Architecture for the Detection of Strongly Connected Components., , , and . ACM Trans. Reconfigurable Technol. Syst., 9 (2): 16:1-16:19 (2016)Exploring Area/Delay Tradeoffs in an AES FPGA Implementation., , and . FPL, volume 3203 of Lecture Notes in Computer Science, page 575-585. Springer, (2004)k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator., , , , , and . EIT, page 257-263. IEEE, (2015)