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Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks.

. IEEE Trans. Computers, 40 (9): 1016-1023 (1991)

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Hardware-Enabled Artificial Intelligence., , , , , and . VLSI Circuits, page 3-6. IEEE, (2018)A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors., , , , , , and . ACM Trans. Comput. Syst., 30 (2): 8:1-8:38 (2012)Issues in the Design and Implementation of Instruction Processors for Multicomputers (Position Statement).. Multithreaded Computer Architecture, volume 281 of The Kluwer International Series in Engineering and Computer Science, Kluwer / Springer, (1994)A Universal Parallel Computer Architecture.. FGCS, page 746-758. IOS Press, (1992)Darwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High Speedup., , , and . HPCA, page 359-372. IEEE, (2019)On-Demand Dynamic Branch Prediction., , , and . IEEE Comput. Archit. Lett., 14 (1): 50-53 (2015)SpArch: Efficient Architecture for Sparse Matrix Multiplication., , , and . HPCA, page 261-274. IEEE, (2020)DSD: Dense-Sparse-Dense Training for Deep Neural Networks., , , , , , , , , and 2 other author(s). ICLR (Poster), OpenReview.net, (2017)Efficient Sparse-Winograd Convolutional Neural Networks., , , and . ICLR (Poster), OpenReview.net, (2018)A Universal Parallel Computer Architecture.. New Generation Comput., 11 (3): 227-249 (1993)Invited.