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Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures., , , , and . IEEE Trans. Computers, 52 (1): 4-20 (2003)Multithreaded algorithms for the fast Fourier transform., , , and . SPAA, page 176-185. ACM, (2000)Towards an Efficient Hybrid Dataflow Architecture Model., , and . PARLE (1), volume 505 of Lecture Notes in Computer Science, page 355-371. Springer, (1991)Dynamic Load Balancers for a Multithreaded Multiprocessor System., , , and . Parallel Process. Lett., 11 (1): 169-184 (2001)The Design and Implementation of TIDeFlow: A Dataflow-Inspired Execution Model for Parallel Loops and Task Pipelining., , , , and . Int. J. Parallel Program., 44 (2): 278-307 (2016)Compiling C for the EARTH multithreaded architecture., , , , , , , and . Int. J. Parallel Program., 25 (4): 305-338 (1997)Self-Avoiding Walks over Adaptive Unstructured Grids., , and . Concurr. Pract. Exp., 12 (2-3): 85-109 (2000)Performance of Interconnection Network in Multithreaded Architectures., , , and . PARLE, volume 817 of Lecture Notes in Computer Science, page 823-826. Springer, (1994)Computing phi-nodes in linear time using DJ graphs., and . J. Program. Lang., (1995)Data locality sensitivity of multithreaded computations on a distributed-memory multiprocessor., , , and . CASCON, page 37. IBM, (1996)