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Trade-off Between Hit Rate and Hit Latency for Optimizing DRAM Cache., , , и . IEEE Trans. Emerg. Top. Comput., 9 (1): 55-64 (2021)An Energy-Oriented Evaluation of Buffer Cache Algorithms Using Parallel I/O Workloads., , и . IEEE Trans. Parallel Distributed Syst., 19 (11): 1565-1578 (2008)RACE: An Efficient Redundancy-aware Accelerator for Dynamic Graph Neural Network., , , , , , , , , и 2 other автор(ы). ACM Trans. Archit. Code Optim., 20 (4): 53:1-53:26 (декабря 2023)Accelerate Hardware Logging for Efficient Crash Consistency in Persistent Memory., , , и . DATE, стр. 388-393. IEEE, (2022)NightWatch: Integrating Lightweight and Transparent Cache Pollution Control into Dynamic Memory Allocation Systems., , , , и . USENIX Annual Technical Conference, стр. 307-318. USENIX Association, (2015)Making Write Less Blocking for Read Accesses in Phase Change Memory., и . MASCOTS, стр. 269-277. IEEE Computer Society, (2012)Temporal characterization of SPEC CPU2006 workloads: Analysis and synthesis., , , и . IPCCC, стр. 11-20. IEEE Computer Society, (2012)Energy Efficient Buffer Cache Replacement for Data Servers., , , и . NAS, стр. 329-338. IEEE Computer Society, (2011)Reducing Read Latency in MLC PCM., и . NAS, стр. 1-6. IEEE Computer Society, (2016)Efficient Hardware-Assisted Crash Consistency in Encrypted Persistent Memory., , , и . DATE, стр. 750-755. IEEE, (2020)