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Electrostatic Characteristics Analysis of Ferroelectric Tunneling Junctions with Different Structures.

, , , and . ICTA, page 112-113. IEEE, (2020)

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Modeling and physical mechanism analysis of the effect of a polycrystalline-ferroelectric gate on FE-FinFETs., , , , , and . Sci. China Inf. Sci., (May 2023)Invited Paper: A Memristor-Based Stateful Majority-Inverter Graph Logic and 1-Bit Full Adder for In-Memory Computing Systems., , , , , and . ICTA, page 95-98. IEEE, (2023)SRAM device and cell co-design considerations in a 14nm SOI FinFET technology., , , , , , , and . ISCAS, page 2339-2342. IEEE, (2013)A Novel General Compact Model Approach for 7nm Technology Node Circuit Optimization from Device Perspective and Beyond., , , , , , , , , and . CoRR, (2019)Accurate simulations of the interplay between process and statistical variability for nanoscale FinFET-based SRAM cell stability., , , , and . ESSDERC, page 349-352. IEEE, (2014)A TCAD-based Study of NDR Effect in NC-FinFET., , , and . ICTA, page 102-103. IEEE, (2020)A comprehensive study of device variability of sub-5 nm nanosheet transistors and interplay with quantum confinement variation., , , and . Sci. China Inf. Sci., (February 2023)Statistical variability in 14-nm node SOI FinFETs and its impact on corresponding 6T-SRAM cell design., , , , and . ESSDERC, page 113-116. IEEE, (2012)Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability., , , , , , and . ESSDERC, page 234-237. IEEE, (2013)Capturing intrinsic parameter fluctuations using the PSP compact model., , , , , , , and . DATE, page 650-653. IEEE Computer Society, (2010)