Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Guest Editorial: IEEE Transactions on Computers and IEEE Transactions on Nanotechnology Joint Special Section on Defect and Fault Tolerance in VLSI and Nanotechnology Systems., , and . IEEE Trans. Computers, 65 (3): 677-678 (2016)Preventing integrated circuit piracy via custom encoding of hardware instruction set., , and . ISQED, page 234-241. IEEE, (2016)A system-level solution for managing spatial temperature gradients in thinned 3D ICs., , , and . ISQED, page 88-95. IEEE, (2013)A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits., , and . ACM Great Lakes Symposium on VLSI, page 529-534. ACM, (2009)Defeating Strong PUF Modeling Attack via Adverse Selection of Challenge-Response Pairs., , , and . AsianHOST, page 25-30. IEEE, (2018)Test Challenges in Nanometer Technologies., , , and . J. Electron. Test., 17 (3-4): 209-218 (2001)Pitfalls of hierarchical fault simulation.. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (2): 312-314 (2004)On linewidth-based yield analysis for nanometer lithography., and . DATE, page 381-386. IEEE, (2009)A study on placement of post silicon clock tuning buffers for mitigating impact of process variation., and . DATE, page 292-295. IEEE, (2009)Peer pressure on identity: On requirements for disambiguating PUFs in noisy environment., , and . NATW, page 1-4. IEEE, (2017)