( en | de | ru )

 

Disambiguation of "Bömmels, Jürgen"

Author of the publication

copydeleteadd this publication to your clipboard
3D SRAM Macro Design in 3D Nanofabric Process Technology.

, , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (7): 2858-2867 (July 2023)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Jürgen Bömmels

Nicolaus Bömmels

Jürgen Schmidt

Experimentelle und numerische Untersuchung dynamisch belasteter Verbundstrukturen mit zellularen metallischen Kernen. Uni Erlangen-Nürnberg, (2009)

Jürgen Braun

An application of Kolmogorov's superposition theorem to function reconstruction in higher dimensions. Uni Bonn, (2009)

Jürgen Meyer

Textvarianz und Schriftkritik: dialogische Schreib- und Lesekultur bei Thomas More, George Gascoigne und John Lyly. Uni Halle-Wittenberg, habilitation, (2009)
 

Other publications of authors with the same name

Constant voltage electromigration for advanced BEOL copper interconnects., , , , , , , and . IRPS, page 2. IEEE, (2015)Impact of process variability on BEOL TDDB lifetime model assessment., , , , and . IRPS, page 5. IEEE, (2015)3D SRAM Macro Design in 3D Nanofabric Process Technology., , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (7): 2858-2867 (July 2023)As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability., , , , , , , , , and 1 other author(s). Microelectron. Reliab., 54 (9-10): 1675-1679 (2014)Evaluation of via density and low-k Young's modulus influence on mechanical performance of advanced node multi-level Back-End-Of-Line., , , , , and . Microelectron. Reliab., (2016)Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects., , , , , , , , , and 1 other author(s). Microelectron. Reliab., (2017)Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow., , , , and . VLSI-SOC, page 34-39. IEEE, (2020)Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies., , , , , , , , , and 6 other author(s). ESSDERC, page 102-105. IEEE, (2014)3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs., , , , and . VLSI-SoC (Selected Papers), volume 621 of IFIP Advances in Information and Communication Technology, page 279-300. Springer, (2020)Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation., , , , , and . Microelectron. Reliab., (2016)