( en | de | ru )

 

Disambiguation of "Carta, Salvatore"

Author of the publication

copydeleteadd this publication to your clipboard
A Holistic Auto-Configurable Ensemble Machine Learning Strategy for Financial Trading.

, , , , and . Comput., 7 (4): 67 (2019)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Alfonso Carta

Corrado Carta

Holger Cartarius

Salvatore Loiero

Fundamentalmetanoia: Untersuchungen zu einem Ort eschato-praktischer Erfahrungs- und Erinnerungskultur. Uni Tübingen, habilitation, (2009)

Salvatore Cusenza

 

Other publications of authors with the same name

Statistical arbitrage powered by Explainable Artificial Intelligence., , , , and . Expert Syst. Appl., (2022)Networks on Chips: A Synthesis Perspective., , , , and . PARCO, volume 33 of John von Neumann Institute for Computing Series, page 745-752. Central Institute for Applied Mathematics, Jülich, Germany, (2005)Using Collaborative Filtering to Overcome the Curse of Dimensionality when Clustering Users in a Group Recommender System., and . ICEIS (2), page 564-572. SciTePress, (2014)Designing Routing and Message-Dependent Deadlock Free Networks on Chips., , , , , , , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 337-355. Springer, (2006)Discovery and representation of the preferences of automatically detected groups: Exploiting the link between group modeling and clustering., , and . Future Gener. Comput. Syst., (2016)Fraud detection for E-commerce transactions by employing a prudential Multiple Consensus model., , , and . J. Inf. Secur. Appl., (2019)Non-Linear Feedback Control for Energy Efficient On-Chip Streaming Computation., , , and . IES, page 1-8. IEEE, (2006)Routing Aware Switch Hardware Customization for Networks on Chips., , , , , and . Nano-Net, page 1-5. IEEE, (2006)Area and Power Modeling for Networks-on-Chip with Layout Awareness., , , , , , and . VLSI Design, (2007)A modular digital VLSI architecture for stereo depth estimation in industrial applications., , and . ISCAS (6), page 481-484. IEEE, (1999)