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Specification and encoding of transaction interaction properties., , и . Formal Methods Syst. Des., 39 (2): 144-164 (2011)Performance optimization of pipelined logic circuits using peripheral retiming and resynthesis., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 12 (5): 568-578 (1993)Retiming and resynthesis: optimizing sequential networks with combinational techniques., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 10 (1): 74-84 (1991)Model checking unbounded concurrent lists., , и . Int. J. Softw. Tools Technol. Transf., 18 (4): 375-391 (2016)Certified Timing Verification and the Transition Delay of a Logic Circuit., , , и . DAC, стр. 549-555. IEEE Computer Society Press, (1992)CNNFlow: Memory-driven Data Flow Optimization for Convolutional Neural Networks., и . ACM Trans. Design Autom. Electr. Syst., 28 (3): 40:1-40:36 (2023)Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface., , , , , , , , , и 3 other автор(ы). ACM Trans. Design Autom. Electr. Syst., 29 (2): 35:1-35:25 (марта 2024)PPU: A Control Error-Tolerant Processor for Streaming Applications with Formal Guarantees., , , , и . ACM J. Emerg. Technol. Comput. Syst., 13 (3): 43:1-43:29 (2017)On computing minimal independent support and its applications to sampling and counting., , , и . Constraints An Int. J., 21 (1): 41-58 (2016)System Level Design: Orthogonolization of Concerns and Platform-Based Design, , , , и . IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (декабря 2000)