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Systematic test program generation for SoC testing using embedded processor.

, , , and . ISCAS (5), page 541-544. IEEE, (2003)

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An efficient BIST method for testing of embedded SRAMs., , and . ISCAS (5), page 73-76. IEEE, (2001)Signal Integrity Loss in SoC's Interconnects: A Diagnosis Approach Using Embedded Microprocessor., and . ITC, page 1093-1102. IEEE Computer Society, (2002)Frequency driven repeater insertion for deep submicron., , , and . ISCAS (5), page 181-184. IEEE, (2004)Multiple Transition Model and Enhanced Boundary Scan Architecture to Test Interconnects for Signal Integrity., , and . ICCD, page 554-. IEEE Computer Society, (2003)Nine-Coded Compression Technique with Application to Reduced Pin-Count Testing and Flexible On-Chip Decompression., , and . DATE, page 1284-1289. IEEE Computer Society, (2004)Systematic test program generation for SoC testing using embedded processor., , , and . ISCAS (5), page 541-544. IEEE, (2003)eUTDSP: a design study of a new VLIW-based DSP architecture., , , and . ISCAS (4), page 137-140. IEEE, (2003)Testing SoC interconnects for signal integrity using extended JTAG architecture., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 23 (5): 800-811 (2004)Extending JTAG for Testing Signal Integrity in SoCs., , and . DATE, page 10218-10223. IEEE Computer Society, (2003)RL-huffman encoding for test compression and power reduction in scan applications., and . ACM Trans. Design Autom. Electr. Syst., 10 (1): 91-115 (2005)