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Memory Devices: Energy-Space-Time Tradeoffs., , , , , , , и . Proc. IEEE, 98 (12): 2185-2200 (2010)The influence of interfacial (sub)oxide layers on the properties of pristine resistive switching devices., , , , , и . NVMTS, стр. 1-4. IEEE, (2018)Kogge-Stone Adder Realization using 1S1R Resistive Switching Crossbar Arrays., , , , и . ACM J. Emerg. Technol. Comput. Syst., 14 (2): 30:1-30:14 (2018)Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory., , , и . ISCAS, стр. 1-5. IEEE, (2019)Controllability of multi-level states in memristive device models using a transistor as current compliance during SET operation., , , и . IJCNN, стр. 1-8. IEEE, (2015)A Complementary Resistive Switch-Based Crossbar Array Adder., , , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 5 (1): 64-74 (2015)A Study of the Electroforming Process in 1T1R Memory Arrays., , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 558-568 (февраля 2023)2022 roadmap on neuromorphic computing and engineering., , , , , , , , , и 49 other автор(ы). Neuromorph. Comput. Eng., 2 (2): 22501 (2022)A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs., , , , , , , , , и 1 other автор(ы). ACM J. Emerg. Technol. Comput. Syst., 18 (2): 32:1-32:25 (2022)Applicability of Well-Established Memristive Models for Simulations of Resistive Switching Devices., , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (8): 2402-2410 (2014)