%0 Journal Article %1 journals/jssc/ChangWHLDHLS03 %A Chang, Kun-Yung Ken %A Wei, Jason %A Huang, Charlie %A Li, Simon %A Donnelly, Kevin S. %A Horowitz, Mark %A Li, Yingxuan %A Sidiropoulos, Stefanos %D 2003 %J IEEE J. Solid State Circuits %K dblp %N 5 %P 747-754 %T A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs. %U http://dblp.uni-trier.de/db/journals/jssc/jssc38.html#ChangWHLDHLS03 %V 38

@article{journals/jssc/ChangWHLDHLS03, added-at = {2022-07-05T00:00:00.000+0200}, author = {Chang, Kun-Yung Ken and Wei, Jason and Huang, Charlie and Li, Simon and Donnelly, Kevin S. and Horowitz, Mark and Li, Yingxuan and Sidiropoulos, Stefanos}, biburl = {https://www.bibsonomy.org/bibtex/2343779bf23809d977d852cfbba47201b/dblp}, ee = {https://doi.org/10.1109/JSSC.2003.810045}, interhash = {21970b4f9efd73a4b3997a4c896a126b}, intrahash = {343779bf23809d977d852cfbba47201b}, journal = {IEEE J. Solid State Circuits}, keywords = {dblp}, number = 5, pages = {747-754}, timestamp = {2024-04-08T10:42:42.000+0200}, title = {A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs.}, url = {http://dblp.uni-trier.de/db/journals/jssc/jssc38.html#ChangWHLDHLS03}, volume = 38, year = 2003 }