( en | de | ru )

 

Disambiguation of "Horowitz, Mark"

Author of the publication

copydeleteadd this publication to your clipboard
A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs.

, , , , , , , and . IEEE J. Solid State Circuits, 38 (5): 747-754 (2003)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Flavio Horowitz

Alexander Horowitz

Pinchas Horowitz

Pinchas Horowitz

Charles Horowitz

 

Other publications of authors with the same name

An Analytical Cache Model., , and . ACM Trans. Comput. Syst., 7 (2): 184-215 (1989)Towards an explanatory and computational theory of scientific discovery, , , , , and . CoRR, (2009)Tiny Tera: a packet switch core., , , , and . IEEE Micro, 17 (1): 26-33 (1997)Rigel: flexible multi-rate image processing hardware., , , , , and . ACM Trans. Graph., 35 (4): 85:1-85:11 (2016)Digital Analog Design: Enabling Mixed-Signal System Validation., , , , and . IEEE Des. Test, 32 (1): 44-52 (2015)A Framework for Adding Low-Overhead, Fine-Grained Power Domains to CGRAs., , , , , , , , , and . DATE, page 846-851. IEEE, (2020)Energy-Performance Tunable Logic., , and . IEEE J. Solid State Circuits, 44 (9): 2554-2567 (2009)Error Control and Limit Cycle Elimination in Event-Driven Piecewise Linear Analog Functional Models., and . IEEE Trans. Circuits Syst. I Regul. Pap., 63-I (1): 23-33 (2016)TANGRAM: Optimized Coarse-Grained Dataflow for Scalable NN Accelerators., , , , and . ASPLOS, page 807-820. ACM, (2019)Timing analysis including clock skew., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (11): 1608-1618 (1999)