%0 Journal Article %1 journals/tcasI/LyuXWLWP21 %A Lyu, Fei %A Xu, Xiaoqi %A Wang, Yu %A Luo, Yuanyong %A Wang, Yuxuan %A Pan, Hongbing %D 2021 %J IEEE Trans. Circuits Syst. I Regul. Pap. %K dblp %N 2 %P 715-727 %T Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers. %U http://dblp.uni-trier.de/db/journals/tcasI/tcasI68.html#LyuXWLWP21 %V 68

@article{journals/tcasI/LyuXWLWP21, added-at = {2022-12-07T00:00:00.000+0100}, author = {Lyu, Fei and Xu, Xiaoqi and Wang, Yu and Luo, Yuanyong and Wang, Yuxuan and Pan, Hongbing}, biburl = {https://www.bibsonomy.org/bibtex/21fcb17b7898eaa0cd80a4ef38867e8b8/dblp}, ee = {https://doi.org/10.1109/TCSI.2020.3038417}, interhash = {273007b228de4f30c4ca5ccb23bfe1f6}, intrahash = {1fcb17b7898eaa0cd80a4ef38867e8b8}, journal = {IEEE Trans. Circuits Syst. I Regul. Pap.}, keywords = {dblp}, number = 2, pages = {715-727}, timestamp = {2024-04-08T16:48:03.000+0200}, title = {Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers.}, url = {http://dblp.uni-trier.de/db/journals/tcasI/tcasI68.html#LyuXWLWP21}, volume = 68, year = 2021 }