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Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers.

F. Lyu, X. Xu, Y. Wang, Y. Luo, Y. Wang, and H. Pan. IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 715-727 (2021)

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Yuanyong Jiao

Xiaoya Luo

Siqi Luo

Quan Luo

Jie Luo

Other publications of authors with the same name

High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers.F. Lyu, Y. Xia, Y. Chen, Y. Wang, Y. Luo, and Y. Wang. IEEE Trans. Very Large Scale Integr. Syst., 30 (4): 544-548 (2022)Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers.F. Lyu, X. Xu, Y. Wang, Y. Luo, Y. Wang, and H. Pan. IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 715-727 (2021)Reconfigurable Multifunction Computing Unit Using an Universal Piecewise Linear Method.F. Lyu, J. Chen, S. Huang, W. Wang, Y. Luo, and Y. Wang. ISCAS, page 2117-2121. IEEE, (2022)Corrections to "Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base".Y. Luo, Y. Wang, Y. Ha, Z. Wang, S. Chen, and H. Pan. IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2222 (2019)An optimized hardware implementation of the CORDIC algorithm.F. Lyu, C. Wu, Y. Wang, H. Pan, Y. Wang, and Y. Luo. IEICE Electron. Express, 19 (21): 20220362 (2022)A CORDIC-Based Architecture with Adjustable Precision and Flexible Scalability to Implement Sigmoid and Tanh Functions.H. Chen, L. Jiang, Y. Luo, Z. Lu, Y. Fu, L. Li, and Z. Yu. ISCAS, page 1-5. IEEE, (2020)Generalized Hyperbolic CORDIC and Its Logarithmic and Exponential Computation With Arbitrary Fixed Base.Y. Luo, Y. Wang, Y. Ha, Z. Wang, S. Chen, and H. Pan. IEEE Trans. Very Large Scale Integr. Syst., 27 (9): 2156-2169 (2019)Effective Plug-Ins for Reducing Inference-Latency of Spiking Convolutional Neural Networks During Inference Phase.X. Chen, X. Yuan, G. Fu, Y. Luo, T. Yue, F. Yan, Y. Wang, and H. Pan. Frontiers Comput. Neurosci., (2021)CORDIC-Based Architecture for Computing Nth Root and Its Implementation.Y. Luo, Y. Wang, H. Sun, Y. Zha, Z. Wang, and H. Pan. IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (12): 4183-4195 (2018)GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number.Y. Wang, Y. Luo, Z. Wang, Q. Shen, and H. Pan. IEEE Trans. Very Large Scale Integr. Syst., 28 (4): 864-875 (2020)

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Disambiguation of "Luo, Yuanyong"

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Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers.

Please choose a person to relate this publication to

Yuanyong Jiao

Xiaoya Luo

Siqi Luo

Quan Luo

Jie Luo

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Luo, Yuanyong"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers.

Please choose a person to relate this publication to

Yuanyong Jiao

Xiaoya Luo

Siqi Luo

Quan Luo

Jie Luo

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Ultralow-Latency VLSI Architecture Based on a Linear Approximation Method for Computing Nth Roots of Floating-Point Numbers.