%0 Journal Article %1 journals/jei/ButtMRL14 %A Butt, Shahzad Ahmad %A Mancini, Stéphane %A Rousseau, Frédéric %A Lavagno, Luciano %D 2014 %J J. Electronic Imaging %K dblp %N 5 %P 053012 %T Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework. %U http://dblp.uni-trier.de/db/journals/jei/jei23.html#ButtMRL14 %V 23

@article{journals/jei/ButtMRL14, added-at = {2022-07-04T00:00:00.000+0200}, author = {Butt, Shahzad Ahmad and Mancini, Stéphane and Rousseau, Frédéric and Lavagno, Luciano}, biburl = {https://www.bibsonomy.org/bibtex/22c013f2c0a965df980f487fc66189276/dblp}, ee = {https://doi.org/10.1117/1.JEI.23.5.053012}, interhash = {3a3b0f272fa6ed89a2c0184acf6b59e3}, intrahash = {2c013f2c0a965df980f487fc66189276}, journal = {J. Electronic Imaging}, keywords = {dblp}, number = 5, pages = 053012, timestamp = {2024-04-08T12:03:29.000+0200}, title = {Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework.}, url = {http://dblp.uni-trier.de/db/journals/jei/jei23.html#ButtMRL14}, volume = 23, year = 2014 }