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Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework.

, , , and . J. Electronic Imaging, 23 (5): 053012 (2014)

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Design of a pseudo-log image transform hardware accelerator in a high-level synthesis-based memory management framework., , , and . J. Electronic Imaging, 23 (5): 053012 (2014)A Non-Intrusive Tool Chain to Optimize MPSoC End-to-End Systems., , and . ACM Trans. Archit. Code Optim., 18 (2): 21:1-21:22 (2021)Synthesis of dependency-aware traffic generators from NoC simulation traces., , , and . J. Syst. Archit., (2016)Methodological Framework for NoC Resources Dimensioning on FPGAs., , , and . FNC/MobiSPC, volume 56 of Procedia Computer Science, page 391-396. Elsevier, (2015)Network Interface Generation for MPSOC: From Communication Service Requirements to RTL Implementation., , and . IEEE International Workshop on Rapid System Prototyping, page 66-69. IEEE Computer Society, (2004)Automatic Generation of Component Wrappers by Composition of Hardware Library Elements Starting from Communication Service Specification., , and . IEEE International Workshop on Rapid System Prototyping, page 47-53. IEEE Computer Society, (2005)Generation of emulation platforms for NoC exploration on FPGA., , and . International Symposium on Rapid System Prototyping, page 186-192. IEEE, (2011)Hardware Context Switch-based Cryptographic Accelerator for Handling Multiple Streams., , , , and . ACM Trans. Reconfigurable Technol. Syst., 14 (3): 14:1-14:25 (2021)Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms., , , , , , , , , and 11 other author(s). J. Syst. Archit., (2016)Interface Optimization During Hardware-Software Partitioning., , , and . CODES, page 75-79. IEEE Computer Society, (1997)